The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in the form of a dynamic random-access memory (DRAM) having a sense amplifier for amplifying the potential difference between a pair of bit lines.
Dynamic random-access memories (DRAMs) are made up of memory elements each composed of one capacitive element and one switching insulated gate field effect transistor connected to the capacitive element. The capacitive element is connected to either the source or drain of the switching insulated gate field effect transistor. For the sake of brevity, however, it is assumed in the following description that the capacitive element is connected to the source of the switching insulated gate field effect transistor. In the DRAMs of such an arrangement, the effect of external noise on a bit line connected to the capacitive element should be reduced as much as possible in order to detect a slight potential variation which is developed over the bit line connecting to the capacitive element through the insulated gate field effect transistor. It is effective to employ a folded bit-line arrangement to minimize the effect of external noise on the bit line. In order to employ the folded bit-line arrangement while maintaining a memory operation margin, however, it is necessary to arrange memory elements such that the same number of memory elements are connected to each of paired bit lines.
FIG. 1 shows a conventional semiconductor memory with the folded bit-line arrangement. In FIG. 1, the semiconductor memory has memory elements arranged such that a plurality of word lines (only word lines WL.sub.2-WL.sub.7 are shown) extend linearly and parallel to each other and a plurality of bit lines (only bit lines BL.sub.1, BL.sub.1 ', BL.sub.2 are shown) extend linearly and parallel to each other at an angle of 90.degree. to the word lines. The paired bit lines, for example the bit lines BL.sub.1, BL.sub.1 ', are disposed adjacent to each other. The memory elements are arranged such that two memory elements are combined into a unit. Namely, as indicated in a memory element region 1.sub.12 shown in an upper central portion of FIG. 1, two memory elements each having a switching transistor with a common drain 12.sub.12 are combined into a unit. Specifically, in memory element region 1.sub.12, a memory element comprising a capacitive element 11.sub.13, a gate 13.sub.13, and the drain 12.sub.12, and a memory element comprising a capacitive element 11.sub.14, a gate 13.sub.14, and the drain 12.sub.12 are positioned symmetrically with respect to the drain 12.sub.12.
A plurality of memory element regions (only memory element regions 1.sub.11 -1.sub.13, 1.sub.21 -1.sub.22, 1.sub.31 -1.sub.33 are shown) are arranged in a matrix. The memory element regions are each positioned after every four word lines in the horizontal direction parallel to the bit lines, and staggered horizontally by two word lines alternately in the vertical direction across the bit lines. Specifically, the upper central memory element region 1.sub.12 is formed such that gate 13.sub.13 of the left memory element is connected to the third word line WL.sub.4 from the left and gate 13.sub.14 of the right memory element is connected to the fourth word line WL.sub.5 from the left. Memory element region 1.sub.21, which is located in the left middle portion, is formed such that gate 13.sub.21 of the left memory element is connected to the first word line WL.sub.2 from the left and gate 13.sub.22 of the right memory element is connected to the second word line WL.sub.3 from the left. Memory element region 1.sub.22, which is positioned adjacent and to the right of memory element region 1.sub.21, is formed such that gate 13.sub.23 of the left memory element is connected to the fifth word line WL.sub.6 from the left and gate 13.sub.24 of the right memory element is connected to the sixth word line WL.sub.7 from the left. Memory element region 1.sub.32, which is located in a lower central portion of FIG. 1, is formed such that gate 13.sub.33 of the left memory element is connected to the third word line WL.sub.4 from the left and gate 13.sub.34 of the right memory element is connected to the fourth word line WL.sub.5 from the left.
The drains of the memory elements positioned along a certain bit line are connected to each other by this bit line. Specifically, the drains 12.sub.11 -12.sub.13 (the drains 12.sub.11, 12.sub.13 are not shown) of the memory elements in the memory element regions 1.sub.11 -1.sub.13 positioned along the uppermost bit line BL.sub.1 are connected to each other by bit line BL.sub.1. Drains 12.sub.21 -12.sub.22 of the memory elements in memory element regions 1.sub.21 -1.sub.22 positioned along the second bit line BL.sub.1 ' from above are connected to each other by bit line BL.sub.1 '.
Because the memory element regions are each positioned after every four word lines in the horizontal direction parallel to the bit lines and staggered horizontally by two word lines alternately in the vertical direction across the bit lines, as described above, there is a dead space region 6 with no memory element region formed in a portion (indicated by the broken line in FIG. 1 ) surrounded by the four memory element regions 1.sub.12, 1.sub.21, 1.sub.22, and 1.sub.32.
It has been proposed to reduce the dead space region 6 by changing the angle between the bit and word lines to an angle other than 90.degree.. According to this proposal, as shown in FIG. 2, the bit lines are arranged to interconnect the drains of memory elements that are successively arrayed obliquely upwardly. Specifically, a drain 12.sub.22 of a memory element region 1.sub.22, which is the second from the upper left, and a drain 12.sub.13 of a memory element region 1.sub.13, which is the first from above and the third from the left, are interconnected by a bit line B.sub.L+1. A drain 12.sub.31 of a memory element region 1.sub.31, which is the third from above and the first from the left, and a drain 12.sub.23 of a memory element region 1.sub.23, which is the second from above and the third from the left, are interconnected by a bit line B.sub.L'.
With the arrangement shown in FIG. 2, the memory element regions are each positioned after every three word lines in the horizontal direction parallel to the bit lines and staggered horizontally by one word line alternately in the vertical direction across the bit lines, thus reducing the dead space region 6 shown in FIG. 1. However, the overall DRAM structure is obliquely oriented toward the upper right as shown in FIG. 3, resulting in new dead space regions 5.sub.1, 5.sub.2 in upper left and lower right portions. As a consequence, the chip area of the DRAM must be larger than necessary for the memory element regions.
Since the memory element regions are each positioned after every three word lines in the horizontal direction parallel to the bit lines and staggered horizontally by one word line alternately in the vertical direction across the bit lines in the memory element layout shown in FIG. 2, the memory element regions 1.sub.11 -1.sub.13', which are the first from above, and the memory element regions 1.sub.21 -1.sub.23, which are the second from above, share a third word line WL.sub.k+2 from the left and a sixth word line WL.sub.k+5 from the left. Therefore, bit lines that are paired are not positioned adjacent to each other. In the illustrated example, inasmuch as the memory element regions 1.sub.11 -1.sub.13 , which are the first from above, do not share any word lines with the memory element regions 1.sub.31 -1.sub.33, which are the third from above, bit lines that are paired are spaced from each other by one bit line. Specifically, a second bit line BL.sub.L from above is paired with a fourth bit line BL.sub.L ' from above, and a third bit line BL.sub.L+1 from above is paired with a fifth bit line BL.sub.L+1, from above.